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20 July 2018, 8:30 am – 5:00 pm | Marina Bay Sands Expo and Convention Centre, Singapore

ZEISS Process Control Innovations Seminar (PCIS)

As the complexity and variety of semiconductor technologies continue to increase, so do challenges for process control technologies. Modern manufacturing techniques are increasingly incorporating novel materials and more complex 3D structures to meet rapidly evolving market demands. Resulting new processes are driving the need for new failure analysis and process control methods.

Please join us at the 1st Annual ZEISS Process Control Innovations Seminar (PCIS) to hear industry experts and leaders from the academic community present case studies for a variety of advanced process control and metrology topics.

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Agenda

8:30 AM

Registration

 

9:00 AM 

Welcome Address

 

9:15 AM

Keynote - Deep Learning in Advanced Semiconductor Manufacturing: Opportunities and Challenges

Dr. Dim Lee Kong, Executive DirectorI2R, IME and A*Star 

9:45 AM

Novel Semiconductor Failure Analysis Workflow using Integrated 3D High-resolution X-ray Microscopy

Mr. Fu Chau, Director of Marketing, Wintech

10:15 AM

Nanoscale XRM: Next-generation X-ray Microscopy for Advanced
Semiconductor Packaging

Dr. Christian Schmidt, Senior Manager, Semiconductor Application Development & Strategy, ZEISS
Luke England, 3D Packaging Manager, Global Foundries
Ingrid DeWolf, Chief Scientist, IMEC

10:45 AM

Tea Break

 

11:15 AM

Device Analysis for Microprocessors in Advanced Process Technology Nodes

Vinod Narang, Engineering Manager, Device Analysis Lab, AMD Singapore

11:45 AM

Focused Helium Ion Beam Applications in Advanced-Node Nanolithography R&D

Dr. Ken Tsai, Associate Professor, National Taiwan University

12:15 PM

Lunch

 

1:30 PM

Submicron Resolution X-ray Microscopy for 3D Inspection and Measurement of Semiconductor Packages

Dr. Allen Gu, Staff Development Engineer, ZEISS

2:00 PM

Multibeam Imaging for Rapid Advanced Circuit Layout Extraction (MIRACLE): Applications & Opportunities

Raghu Nayak, Segment Solutions Manager, ZEISS

2:30 PM

Summary and Closing

 

2:45-5:00 PM

Cocktail Reception 

 

Abstracts

10:15 AM — Nano-scale XRM: Next-generation X-ray Microscopy for Advanced Semiconductor Packaging
Dr. Christian Schmidt, Senior Manager, Semiconductor Application Development & Strategy, ZEISS, Luke England, 3D Packaging Manager, Global Foundries, Ingrid DeWolf, Chief Scientist, IMEC

With the growing complexity and interconnect density of modern semiconductor packages, package level FA is also facing new challenges and requirements. 3D X-ray Microscopy (XRM) is considered a key method to fulfill these requirements and enable high success FA yield. After a short introduction into the basic principles of lab-based X-Ray tomography, two different approaches of X-ray investigations are discussed and an integration into the daily FA flow is proposed. In the first example, fault isolation on a fully packaged device is demonstrated using a stacked die device. In the second example, a newly developed sample preparation flow in combination with nanoscale 3D X-ray microscopy for chip-package-interaction and back-end-of-line feature imaging is introduced.


11:15 AM — Device Analysis for Microprocessors in Advanced Process Technology Nodes
Vinod Narang, Engineering Manager, Device Analysis Lab, AMD Singapore

Semiconductor Process Technology continues its strong innovation tradition with Moore’s law pushing Microprocessor devices into deep nano-scale realm. Device Analysis plays a significant role in the innovation cycle especially during Process Development, First Silicon Bring-up, Yield Improvement and Product Reliability Qualification to identify root cause of failures. The corrective fixes by design and process teams closes the loop. A typical failure analysis flow includes non-destructive testing followed by fault isolation to isolate the defective region and physical failure analysis to identify the physical defect causing device failure.

This talk provides an overview of various physical failure analysis tools. The aim of the presentation is to provide sufficient depth for each topic including relevant case studies to emphasize the key points related to each methodology. Finfet technology challenges and possible solutions are also discussed. Relevant future directions and roadmap which are critical to tackle ever advancing process technology and product complexity are highlighted.