The EUV lithography has been employed to manufacture the state-of-the-art semiconductor devices. This talk will review the technical review of the EUV blanks, which is one of the key EUV eco system.

May 18
15:30 p.m. – 16:00 p.m.

In this talk, we investigated an extension of the existing mask repair product line to also address particle defects. The resulting tool for particle removal leverages the know-how on defect repair using e-beam based repair schemes with a novel in-situ manipulator to remove particles, including real-time observation by scanning electrode microscopy. This talk will focus primarily on successfully demonstrating defect removal, reviewing the area of interest by SEM and showing no collateral damage being observed by SEM-EDX (Energy Dispersive X-ray) analysis.

May 18
16:00 p.m. – 16:30 p.m.

Scaling trends in the semiconductor industry towards smaller technology nodes and features sizes are continuing and first consumer products manufactured with the help of EUV technology are already on the market. During the talk the latest results of high-end EUV repairs carried out on the next generation photomask repair tool MeRiT® LE will be presented.

May 18
16:40 p.m. – 17:10 p.m.

Abstract to come

May 19
15:30 p.m. – 16:00 p.m.

The industry widely utilizes 193nm lithography for high end chip manufacturing. Together with the introduction of EUV lithography and application of mix & match technologies the mask specifications for 193nm high end masks tighten continuously. Source Mask Optimization technologies are applied to meet the printing targets. As result mask designs as well as scanner illumination schemes become more complex. This talk will demonstrate how ZEISS AIMS® 1x-193i high-end system supports our customers to meet the challenges of increasing complexity, tighter mask specification control and high productivity.

May 19
16:00 p.m. – 16:30 p.m.

In the ever-lasting development towards smaller nodes, DUV lithography has recognized the importance of understanding the mask contribution to the wafer printing, for which the error tolerances are constantly tighten with every node. The same process will be necessarily undergone by EUV lithography, for which the more complex nature of the mask and of the imaging process will require a tighter control of all components concurring to the manufacturing of the chip as the nodes will be scaling down. In this talk, we demonstrate how AIMS® EUV supports our customers to meet the challenges of EUV lithography.

May 19
16:40 p.m. – 17:10 p.m.