Wafer alignment mark placement

accuracy impact on the layer-to-layer overlay performance

Richard van Harena, Steffen Steinertb, Orion Mouraillea, Koen D’havéc, Leon van Dijka, Jan Hermansc, Dirk Beyerb

aASML, Flight Forum 1900 (no. 5846), 5657 EZ Eindhoven, The Netherlands
bCarl Zeiss SMT GmbH, Carl-Zeiss-Promenade 10, 07745 Jena, Germany
cIMEC, Kapeldreef 75, B-30001, Leuven, Belgium


It has been demonstrated that the mask-to-mask overlay contribution can be fully characterized by off-line measurements on the PROVE® mask registration tool. This characterization includes the impact of the marks that are used for reticle alignment inside the scanner. This is an important aspect since the scanner is blind to the features inside the image field and intra-field adjustments are only based on measurements of the reticle alignment marks. The off-line determined mask-to-mask overlay was compared with the measured on-wafer results and a perfect correlation (R2 > 0.96) was found.

The residual mismatch was around 0.6-nm, which is 30% of the dedicated chuck overlay performance of the scanner that was used. These results enable feed-forward corrections to the scanner to improve the intra-field overlay performance or to predict the intra-field overlay originating from mask writing errors (computational overlay).

We recently extended the work to the layer-to-layer overlay impact by considering the mask writing error of a wafer alignment mark. This wafer alignment mark was exposed in the first layer. Apart from the reticle writing error of the wafer alignment mark itself, the reticle alignment contribution performed on dedicated reticle alignment marks inside the scanner plays an important role as well. The actual position of the selected wafer alignment mark is also impacted by the reticle alignment model corrections at that specific field location. Only when both contributors are considered, the layer-to-layer overlay can be predicted accurately. In this scenario, the layer-to-layer overlay is measured back to the layer in which the alignment marks were defined. This is referred to as the direct alignment use-case.

In this paper, we further investigate the direct alignment use-case in relation to the layer-to-layer overlay. Apart from the reticle writing error and the reticle alignment corrections, the actual placement of the wafer alignment mark during
exposure can also be affected by other applied corrections. We will present experimental results of the layer-to-layer overlay as function of the applied automated process corrections on the wafer alignment mark location printed in the first layer. It is shown that the wafer alignment sensor impact should be considered as well in the interpretation of the results. We finally present a strategy to control these kinds of overlay errors.

Keywords: Registration Error, Overlay, Computational Overlay, Reticle, Mask, Direct wafer alignment, Wafer alignment mark, APC, Feed-Forward

Proceedings Volume 11178, Photomask Technology 2019; 1114811 (2019) https://doi.org/10.1117/12.2536270
Event: Photomask Technology + EUV Lithogrpahy, 2019, Monterey, California, United States

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