We will welcome you with an opening speech introducing the portfolio of photomask solutions with focus on innovations in the Repair and EUV measurement field.  

EUV lithography is being used for the production of 7-nm and 5-nm node logic devices and recently major memory manufacturers also revealed the use of EUV in the latest DRAM generation. With EUV it has become important to quantify the patterning requirements, thru the EPE metric, since photon and resist stochastics are becoming more dominant. Depending on the exact patterning method, the allowed maximum edge placement error (EPE) is driven towards single digit numbers (7-nm to 9-nm) and it thorough understanding of the error budget is required to achieve and reduce these numbers further.

In the presentation the EPE budget will be explained and it will be shown how a holistic patterning approach can be used to minimize overlay and EPE of the final pattern. The holistic approach combines advanced wafer metrology and scanner actuator control using computational lithography. The metrology solutions include optical and e-beam based methods to determine the pattern overlay and CD on device scale. Based on data obtained for logic and memory use cases we see that the main contributors of the EPE budget are: local errors, overlay errors, optical proximity errors and CD variation. The Mask is a known to contribute to intra-field fingerprints for both CD and registration, but recent studies also have shown that local errors are very significant and with this improvements of all these mask parameters is needed to secure the next step in EPE.

The presentation will show that controlling wafer CDU - even if the CDU is in spec - can reduce process defect failure probability and by that can reduce the yield loss.

Off the beaten path: a novel approach to fight defectivity with a never been there efficiency.

Scaling trends in the semiconductor industry towards smaller technology nodes and features sizes are continuing and first consumer products manufactured with the help of EUV technology are already on the market. During the talk the latest results of high-end EUV repairs carried out on the next generation photomask repair system MeRiT® LE will be presented.

Automation is more and more a key success factor in mask manufactruing. We will provide a short overview on the range of Automation Solutions for Mask Repair. One solution, the Advanced AutoRepair provides a fully automated workflow of Photomask repair. DataScoop is a unified health monitoring and analysis tool for MeRiT® and PRT. The Large Defect Repair application provides improved operational throughput and repair controllability for the repair of defects up to 4x4µm^2 size.

Fully automated processes in mask manufacturing offer significantly better yields, output, cycle times, operating costs and flexibility than manually driven ones. In order to achieve this, a wide range of digital solutions can bridge the gaps between equipment by use of overarching and integrating solutions as well as solutions dedicated to individual processes. Digital support, however, comprises more than manufacturing processes and can go far beyond this. It is the embedding element that keeps the engine running optimally.

The industry usually focusses on high-end market driven by smaller feature sizes and continuously tightening mask specifications. However, most of the mask volume goes into larger technology nodes and serves the needs of the mature market. In that market segment high productivity at low cost and high yield are the main challenges. In this talk ZEISS will present solutions that addresses these challenges to ensure an effective mask qualification using AIMS® technology.

For EUV lithography the mask-to-mask contribution as part of the overall on-product overlay budget can not be neglected anymore. In order to reach the required pattern placement at mask, state of the art registration systems enable the calibration of latest generation writing tools by a new level of metrology precision as well as dense sampling schemes. Additional overlay contributors can be adressed by measurements of front and mask backside flattnes. Even more, the unique stage accuracy of registration metrology tools allows for the precise location of native EUV defects as needed for defect mitigation strategies.